The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for fin-type field effect transistors (FinFETs) having low source/drain (S/D) contact resistance.
A FinFET is a type of non-planar transistor formed on a substrate. FinFETs are formed from a three-dimensional elongated fin that extends away from a major surface of the substrate. A gate structure is wrapped around a central portion of the fin such that the central portion forms a channel region of the FinFET device. The portions of the fin that are not under the gate structure form the source and drain regions. The elongate fin-shaped channel allows multiple gate structures to operate on a single transistor.
S/D contact resistance is a measure of the ease with which current can flow across the interface between a metal contact and the semiconductor material that forms the S/D region. As non-planar devices, FinFETs extend Moore's law allowing semiconductor manufacturers to create CPUs and memory modules that are smaller, perform faster, and consume less energy. However, smaller devices result in smaller gate pitch, which can negatively impact the device's S/D contact resistance performance.